Structure-Driven Equivalence Verification for Circuits Optimized by Retiming and Combinational Synthesis

Sequential optimization techniques fall in two broad categories: state-based and structure-based [4]. Structurebased techniques optimize a circuit netlist by interleaving retiming and combinational synthesis in different ways to improve design metrics such as delay, area, and power. Examples of such optimizations include among others: peripheral retiming [7], architectural retiming [6], and iterative retiming and resynthesis [2]. While structure-based synthesis algorithms can handle relatively large netlists, current sequential equivalence verification algorithms are not as scalable and as robust. We believe that the absence of a reliable verification framework for such sequential optimization hinders their industrial acceptance despite potential improvements in design quality.